Category cad
- abc-1.01.20200108 - system for sequential logic synthesis and verification
- dxf2gcode-20191025 - tool to convert 2D (dxf, pdf, ps) files to gcode
- freehdl-0.0.7p5 - open-source (C++ generating) VHDL simulator
- fritzing-0.9.2bp6 - interactive electronics designing software
- geda-gaf-1.6.0p21 - suite of tools for electronic design automation
- gerbv-2.7.0p0 - viewer for Gerber (RS-274X) files
- gnucap-0.35p9 - Gnu Circuit Analysis Package
- graywolf-0.1.6p1 - placement tool used in VLSI design
- gtkwave-3.3.108 - GTK+-based electronic waveform viewer
- kicad-5.1.7v0 - schematic and PCB editing software
- kicad-footprints-5.1.7 - footprint modules for KiCad
- kicad-i18n-5.1.7 - language translations for KiCad
- kicad-packages3D-5.1.7 - 3D packages for KiCad
- kicad-symbols-5.1.7v0 - symbol modules for KiCad
- kicad-templates-5.1.7 - templates for KiCad
- libngspice-31 - ngspice shared library, based on Berkeley SPICE
- librecad-2.2.0rc1p1 - 2D CAD program
- magic-8.3.137 - interactive system for VLSI circuit layouts
- necpp-1.2.3p8 - NEC2++ antenna simulator
- netgen-1.5.171 - tool for netlist comparison (LVS) and format manipulation
- ngspice-31 - circuit simulator, based on Berkeley SPICE
- oce-0.18.3 - C++ 3d modeling library
- openscad-2021.01 - the programmer's solid 3D CAD modeller
- opensta-2.2.0p0 - Parallax Static Timing Analyzer
- pcb-4.1.3p0v0 - printed circuit board layout tool
- pcb2gcode-2.1.0 - tool for isolation, routing, and drilling of PCBs
- qcad-3.24.3.0p1 - Qt-based 2D CAD system
- qelectrotech-0.70p0 - electric diagrams drawing tool
- qflow-1.4.83 - full end-to-end digital synthesis flow for VLSI ASIC designs
- qrouter-1.4.84 - multi-level, over-the-cell maze router for VLSI design
- qucs-s-0.0.22p0 - an universal GUI for SPICE and not-SPICE circuit simulators
- tkgate-2.1 - Tcl/Tk based digital circuit editor and simulator
- xcircuit-3.7.57 - circuit drawing and schematic capture
- xnecview-1.37 - NEC2 antenna simulator visualizer
- xschem-2.9.2 - hierarchical schematic capture program
- yosys-0.9p1 - framework for Verilog RTL synthesis