The cad/yosys port
yosys-0.70 – Yosys Open SYnthesis Suite (cvsweb github mirror)
Description
This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.WWW: https://github.com/YosysHQ
Readme
+-------------------------------------------------------------------------------
| Running ${PKGSTEM} on OpenBSD
+-------------------------------------------------------------------------------
High RAM consumption
====================
Synthesizing FPGAs is a memory intensive task. Even relatively small designs
might lead to errors such as
libc++abi: terminating due to uncaught exception of type std::bad_alloc
Abort trap (core dumped)
In this case, editing /etc/login.conf(5), to increase the parameters
default:\
datasize-max=8192M:\
datasize-cur=8192M
helps. Obviously, it is required to log off and on again, before it has any
effect on re-running YoSys.
Maintainer
Thomas Dettbarn
Only for arches
aarch64 alpha amd64 arm hppa i386 mips64 mips64el powerpc powerpc64 riscv64 sparc64