The cad/abc port

abc-1.01.20210519 – system for sequential logic synthesis and verification (cvsweb github mirror)

Description

ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.

WWW: https://people.eecs.berkeley.edu/~alanmi/abc