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The cad/netgen port

netgen-1.5.171p3 – tool for netlist comparison (LVS) and format manipulation (cvsweb github mirror)

Description

Netgen is a tool for comparing netlists, a process known as LVS (Layout
vs. Schematic). This is an important step in the VLSI IC design flow,
ensuring that the geometry that has been laid out matches the expected
circuit.

Netgen is considered complete and competitive with commercial-grade
tools. Code was added to handle device properties and to resolve
parallel combinations of devices whether individually instantiated
or implied through the use of the "M" property. Serial and parallel
networks of passive devices are analyzed and compared between networks.
WWW: http://opencircuitdesign.com/netgen/

Maintainer

Alessandro De Laurenzis

Categories

cad lang/python lang/tcl x11/tk

Library dependencies

Build dependencies

Run dependencies

Files

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