iverilog-11.0p1 – Verilog simulation and synthesis tool (cvsweb github mirror)

Description

Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code writen in Verilog (IEEE-1364) into
some target format. For batch simulation, the compiler can generate an
intermediate form called vvp assembly. This intermediate form is
executed by the "vvp" command. For synthesis, the compiler generates
netlists in the desired format.

The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2005. This is a
fairly large and complex standard, so it will take some time for it to
get there, but that's the goal.

WWW: https://steveicarus.github.io/iverilog/

Maintainer

The OpenBSD ports mailing-list

Only for arches

aarch64 alpha amd64 arm hppa i386 mips64 mips64el powerpc powerpc64 riscv64 sh sparc64

Categories

devel lang

Library dependencies

Build dependencies

Reverse dependencies

Files

Ports Readmes 7.52, created on 2024-12-18, powered by Dancer 1.3521