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The lang/verilator port

verilator-5.044 – very fast free Verilog HDL simulator (cvsweb github mirror)

Description

Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.
WWW: https://www.veripool.org/wiki/verilator/Intro

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The OpenBSD ports mailing-list

Only for arches

aarch64 alpha amd64 arm hppa i386 m88k mips64 mips64el powerpc powerpc64 riscv64 sh sparc64

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