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The lang/myhdl port

myhdl-0.11.49 – Python as a hardware description and verification language (cvsweb github mirror)

Description

MyHDL is an open source Python package that lets you go from Python to
silicon. With MyHDL, you can use Python as a hardware description and
verification language. Furthermore, you can convert MyHDL code, that was
developed towards implementation, to Verilog and VHDL automatically, and
take it to a silicon implementation from there.
WWW: https://www.myhdl.org/

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lang lang/python

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