The emulators/spike port
spike-1.1.0 – RISC-V ISA simulator (cvsweb github mirror)
Description
Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts.WWW: https://github.com/riscv-software-src/riscv-isa-sim
Maintainer
Jasper Lievisse Adriaanse
Only for arches
aarch64 alpha amd64 arm hppa i386 mips64 mips64el powerpc powerpc64 riscv64 sparc64
Not for arches
i386
Broken
on powerpc: internal 'exception trap_instruction_page_fault' at runtime